# Posts belonging to Category Radio Frequency (RF)

## L-Network impedance matching

Impedance matching is an everyday problem for RF circuit designers. The L-Network is one of the easiest lossless ways of matching a low source impedance to a higher load impedance. This article shows how they work and how to design them.

Matching a transistor amplifier’s low output impedance with the higher impedance of an antenna (typically 50 or 75 Ohms) is just one everyday example of where an L-Network can be used. For this article, we are going to design an L-Network that matches a 75 Ohm source (function generator) with a 1 kΩ load (resistor).

To make it easier for you to understand how this network works, I will present the complete circuit first, explain how it works and then explain how the values are being calculated. Here is the finished L-Network:

L-Network matching 75 Ohms source impedance to 1000 Ohms load impedance

RS = Source Resistance (75 Ohms)
Ls = Series inductance (j263)
Cp = Parallel Capacitance (-j284)

Don’t be frightened by the little “j” in front of the values, in case you have never seen it. The letter “j” in electronics engineering stands for the imaginary unit. Adding “j” to a reactance is basically the so-called “vector notation.” A positive value indicates an inductive reactance and a negative value is always a capacitive reactance. If you are not used to it, you can just think of Ls as an inductor with a reactance of 263 Ohms and of Cp as a capacitor with a reactance of 284 Ohms.

Note that the reactance of a capacitor and an inductor is frequency dependent. Therefore, this circuit does not work well over a large bandwidth.

This circuit makes the 1000 Ohms load ‘look’ like a 75 Ohms load to the source. But how does it work? To answer this question, we have to look at the equivalent circuit. For that, we will reduce the overall circuit to simpler elements, step by step.

Let’s start with Cp and RL. They are in parallel. The overall impedance of two resistors is calculated as follows:

$R = \frac{R_1 * R_2}{R_1 + R_2}$

Likewise, the resulting complex impedance of a resistor and a capacitor can be calculated as follows:

$Z = \frac{Xc * R}{Xc + R}$

In our case, we get:

$Z = \frac{X_c * R_L}{Xc + R_L} = \frac{-j284 * 1000}{-j284 + 1000} = 75-j263$

75 is the real part in Ohms and -j263 is a capacitive reactance of 263 Ohms. That means the capacitor and resistor in parallel will act like a resistor with 75 Ohms and a capacitor with 263 Ohms reactance in series.

Equivalent circuit for Cp and RL

Now if you insert that back into the original circuit and have a close look at it, you may notice something. Look at the reactance of Cp and Ls.

Overall equivalent circuit after reducing Cp and RL to a series equivalent circuit

Correct, the reactance of both the capacitor and the inductor are the same, just with different vectors. If you have never worked with a complex impedance beforehand, you will now be amazed by how much easier it makes things. We can simply add the reactances together, and since 263 + -263 is zero, we only have the 75 Ohms load resistance left. Yes, it’s that simple, the source ‘sees’ the 1 kΩ load as a 75 Ω load.

Overall equivalent circuit of the L-Network

An often-welcomed side effect is that this L-Network acts as a low-pass filter. So, if it’s used to match a low transistor amplifier impedance directly to the higher antenna impedance, one suppresses harmonics at the same time.

If one wishes to have a high-pass characteristic, one can simply switch the positions of the inductor and the capacitor. It really changes nothing. The impedance values, of course, need to be properly adjusted in that case.

Let’s talk about how to design a circuit like this from scratch. We will use the above values, source impedance of 75 Ohms and load impedance of 1000 Ohms at a frequency of 16 MHz. The frequency doesn’t matter until the end when we have to pick actual values for Ls and Cp.

The first thing we have to calculate is the quality factor, or Q factor. It describes how under-damped an oscillator or resonator is, or equivalently, characterizes a resonator’s bandwidth relative to its center frequency. The Q of an L-Network is calculated as follow:

$Q = \sqrt{\frac{R_{Load}}{R_{Source}}-1}$

RSource = Source Resistance

With our values plugged into the equation, we get the following:

$Q = \sqrt{\frac{1000}{75}-1} = 3.512$

So 3.512 is our Q. The rest is just as simple. To get the needed impedance of the inductor, we use the following formula:

$X_L = Q*R_{Source} = 3.512 * 75 = 263$

That means the inductor needs to have an impedance of 263 Ohms at the desired frequency. We can write this as j263 to make sure it’s apparent that it is an inductive reactance. The impedance of the capacitor needs to be the load resistance divided by the Q factor.

$X_C = \frac{R_{Load}}{Q} = \frac{1000}{3.512} = 284$

Again, this means that the impedance of the capacitor at the desired frequency needs to be 284 Ohms. Using the vector notation, we write -j284 to indicate that it is a capacitive impedance.

Okay, now we need to find actual values for the inductor and the capacitor. To be able to calculate either one, we need to settle on an operating frequency. For this article we will use 16 MHz. Using the following formulas, we can find the actual values for the parts at the desired frequency:

$L = \frac{X_L}{\omega} = \frac{263}{2 \pi (16*10^6)} = 2.6 \mu H$

That means our inductor needs to have a value of 2.6 μH. I chose a value of 2.2 μH as it is a common value I had in stock. Since the circuitry itself in real life usually contains what’s called parasitic inductance, it won’t throw the circuit off by far. Next up is the capacitor:

$C = \frac{1}{\omega X_C} = \frac{1}{2 \pi (16*10^6) 284} = 35 pF$

Instead of 35 pF, I used a 33 pF capacitor. Not only is it a more common value, we can again assume a little bit of stray capacitance by the remaining circuit.

75 Ohms to 1000 Ohms L-Network characterized with a return loss bridge

I used a return loss bridge, a signal generator and an oscilloscope to verify the performance of this circuit. And sure enough, it acts just like a 75 Ohm resistive terminator at about 16 MHz. The exact frequency for best operation turned out to be roughly 16.1 MHz.

Confirming the performance of the 75 Ohms to 1000 Ohms L-Network using the Teledyne LeCroy HDO4024

Update (04/06/2013): I previously wrote that one can not match a high impedance source to a low impedance load. That is incorrect. Naturally, it works perfectly fine the other way around. One only has to switch the position of the load and the source.

KJ6QBA took out the time to simulate this circuit using LTspice. He also simulated the same circuit used in reverse to match a 1000 Ohm source to a 75 Ohm load. Here’s the result:

LTspice simulation of the L-Network provided by KJ6QBA

## Review: Analog Devices ADF4360 PLL Synthesizer

The ADF4360 series from Analog Devices is a a family of integer-N-synthesizer chips with on-board VCOs. Since the chips cover all amateur radio bands between 4m – 13 cm and are rather inexpensive, they are predestined to be used in homebrew amateur radio equipment.

Not too long ago I reviewed ADI’s wideband PLL synthesizer ADF4351 with integrated low phase noise VCO. The ADF4360 series family of synthesizer chips is very similar. The primary difference is their restricted frequency coverage and thus much lower price.

The ADF4360 is an integrated integer-N synthesizer with an integrated voltage controlled oscillator (VCO). The center frequency is set by external inductors. There are 9 chips in the family with 8 different frequency ranges. The frequency range are as follows:

Even though the ADF4360-8 and ADF4360-9 have the same frequency range, they are a bit different. The ADF4360-9 has an auxiliary divider with division ranges from 2 to 31 on board. The ADF4360-8 has – just like all other ADF4360 – a hardware power down input (CE).

Analog Devices kindly sent me one of their Evaluation Kits for the ADF4360-9 (EV-ADF4360-9EB1Z) for review and evaluation [1].

EV-ADF4360-9EB1Z evaluation board from Analog Devices

What I intend to use this chip in is called a Fox-Hunt transmitter. It has very little to do with hunting actual foxes and actually relates to a common radio direction finding exercise. The way this works is that a small transmitter (the “fox”) is hidden somewhere and a group of people will attempt to locate the transmitter. Whoever finds the transmitter first, wins the game.

I want to build a very small transmitter for the 2m amateur radio band (~145 MHz) with just a few miliwatts of output power. With such a low power VHF transmitter, a radio direction finding exercise could be conducted in a small area like a park, or even more challenging, with several transmitters at the same time. A microcontroller is supposed to be in charge of setting the frequency and keying the required station identification (call-sign of the control operator) as required by the FCC.

But now back to the ADF4360. The chip has an SPI compatible 3-wire interface, operates between 3 – 3.6 Volts and its inputs are 1.8 V logic compatible. In other words: this chip will interface with pretty much any microcontroller out there. My project will probably be Atmel AVR or MSP430 based and I program in C. However, I will write example code for Arduino (AVR) / Energia (MSP430) for folks who would like to experiment with it more easily.

I looked at the output spectrum of the ADF4360-9 set to 400 MHz on a Teledyne LeCroy HDO6054. The phase frequency detector (PFD) frequency is 200 kHz and you can clearly see spurs 200 kHz spaced to both sides of the carrier. The spurs are smaller than -70 dBc and, to be fair, the ADF4360-9 is not correctly terminated. The IC has a differential output and the datasheet warns that the performance of the output signal may be degraded if not both ports are properly terminated with 50 Ohms. In my case, only one port is fed into the 50 Ohm port of the scope. The other port is open.

Output spectrum of a ADF4360-9 at 400 MHz with a 200 kHz PFD frequency. Clearly visible, the spurs 200 kHz left and right from the carrier

In any case, -70 dBc is a lot of attenuation. As a matter of fact, the output signal could be transmitted the way it is over the air. The FCC demands in 74 CFR 97.307 (e) that “the mean power of any spurious emission from a station transmitter or external RF power amplifier transmitting on a frequency between 30 – 225 MHz must be at least 60 dB below the mean power of the fundamental.” This is clearly the case.

The eval board comes with a very comfortable software, just like the ADF4351 did. It is very nice to be able to manipulate all registers and parameters and watch what happens right away.

So what’s next? I will design the circuit, design a PCB, and write the necessary software code for the little VHF tracker (“fox”). The project will be an open hardware project. That means you will be able to use my project free of charge for personal use. As soon as that is done, I will post a new article with the entire project in it. Stay tuned!

## Review: Texas Instruments CC2531 USB Evaluation Module Kit

The CC2531 is the second generation ZigBee/IEEE 802.15.4 compliant System-onChip with an optimized 8051 MCU core and radio for the 2.4 GHz unlicensed ISM/SRD band from Texas Instruments. But what good is it, really?

To make the evaluation of the CC2531 a bit easier, TI put together the CC2531EMK. The CC2531EMK is a an evaluation kit containing a USB dongle built around the CC2531 [1]. Element 14 sent me a CC2531 USB dongle development kit as part of a RoadTest. RoadTest is a program sponsored by Element 14 that promotes real product reviews by real people like us.

CC2531 USB Dongle plugged into my Netbook

#### Overview and Tech Specs

The CC2531 is a USB-Enabled System-On-Chip Solution for 2.4-GHz IEEE 802.15.4 and ZigBee applications in a tiny 6-mm × 6-mm QFN40 package. The chip is 8051-based, has 8 kB of RAM and is available with either 128 kB (CC2531F128) or 256 kB (CC2531F256) of In-System-Programmable (ISP) flash [2].

Since the chip is compliant with various national and international standards, namely ETSI EN 300 328 and EN 300 440 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T-66 (Japan), products built around this chip do not need to worry about national and international compliance. With a maximum output power of 4.5 dBm (2.82 mW), the chip is perfect for small range communication.

The CC2531 provides extensive hardware support for packet handling, data buffering, burst transmissions, data encryption (AES Security Coprocessor), data authentication, clear channel assessment, link quality indication (Accurate Digital RSSI/LQI) and packet timing information.

With 21 general-purpose I/O Pins and a 12-Bit ADC with 8 channels and configurable resolution, the chip supplies plenty of peripherals for external circuitry.

#### Unboxing

The box contains the CC2531EMK USB dongle and a quick start guide. The quick start guide is straight to the point and easy to understand.

CC2531EMK on top of the quick start quide

While reading the quick start guide, I realized that there is no way to program the MCU’s flash memory without the use of an external debugger. Such a debugger needs to be purchased individually. In other words, one can’t program the CC2531EMK without buying a debugger like the CC Debugger, for instance [3].

#### Software Installation

To get started with the CC2531 dongle, one needs to install the appropriate drivers. The driver package comes bundled with a packet sniffer application which TI provides. Be careful to use the correct URL for the download. It is not – as falsely indicated in the quick start manual – http://www.ti.com/packetsniffer! The correct URL is: http://www.ti.com/tool/packet-sniffer

Download and install the software package from the previously mentioned URL. After the installation is complete, your PC should automatically recognize your CC2531 dongle and apply the pre-installed drivers.

Upon start-up of the packet sniffer software, one has to select the protocol one intends to use. For the CC2531, the only possible options are “IEEE 802.15.4/ZigBee” and “ZigBee RF4CE”.

TI Packet Sniffer Application

The next thing that needs to be selected is, of course, the correct RF channel.

SmartRF Packet Sniffer Channel Selection

One can specify which fields of the captured traffic that the SmartRF packet sniffer software displays.

SmartRF Packet Sniffer filter selection

#### Summary

This is a nice piece of kit to evaluate the CC2531. However, the kit alone is not of much use. To actually accomplish anything useful, one needs at least one additional IEE 802.14 / ZigBee device. And in order to program it, an extra programmer / debugger is required.

I will go ahead and buy a CC Debugger and post again soon with my experience of the CC2531EMK in an actual (demo) application.

[1] CC2531EMK, Newark: http://www.newark.com/

[2] CC2531 Datasheet, TI: http://www.ti.com/

[3] CC Debugger, Newark: http://www.newark.com/

## DIY Passive Probe for the GHz range

Passive probes for the GHz range are costly and it’s usually not too economical to invest into one if you’re just a hobbyist. But regular, cheap probes will not work on signals in the GHz range. So is there a homebrew solution? Yes, there is, check it out!

Every passive probe and every piece of coax cable has a specific capacitance. This fact is simply given by the laws of physics. A Teledyne LeCroy PP016 (300 MHz BW) probe, for instance, has a maximum input capacitance of 12 pF in the 1:10 position. Probes rated for smaller bandwidths often have an even higher input capacitance.

12 pF doesn’t sound like much at all. At 1 GHz, though, this capacitance acts like a load with a resistance of 13.26 Ohms. Correctly, this would be referred to as a reactance and not as a resistance, though. Needless to say, 13.26 Ohms is way too low and, in most cases, will put too much weight on whatever it is we measure. Remember, our goal is usually to have the highest possible impedance to put the least possible load on the stage we are testing.

Of course there are commercial solutions for this problem available. Look at the Teledyne LeCroy PP066 ‘High Bandwidth Passive Probe’ for up to 7.5 GHz, for instance [1]:

Teledyne LeCroy PP066 transmission line for up to 7.5 GHz

The probe really looks like a modified SMA connector with a tip attached to the center pin and a grounding pin connected to the shield. A probe like this costs more than an inexpensive entry-level oscilloscope itself. So can we built something like this at home? Obviously I wouldn’t write this article if we couldn’t, so here is what I did.

While looking for a good starting point, I stumbled across my box of small semi-rigid coax jumpers [2]. Semi-rigid cable has a very low specific capacitance of around 0.1 pf/mm. That would mean a short piece of about 2.5 cm or 1″ would barely have 2.5 pF of capacitance. At 1 GHz, that would mean a reactive load of 63.66 Ohms. Since most circuit stages in that frequency range work with a impedance of 50 Ohms anyway, the line impedance is high compared to the 50 Ohms. So how do we transform the coax into a cheap probe?

Semi-rigid coax cable with SMA connectors

The first thing I did was carefully stripping a piece of the copper shield off. I used a normal pocket knife for this purpose. To my surprise, it’s fairly easy to cut the shield without damaging the dielectric too much. Next, I stripped some of the dielectric to expose a few mm of the center conductor.

Cut-off semi-rigid coax cable

The only thing that was missing now was a ground lead. Thanks to the solid copper shield, that was an easy task. I simply soldered a piece of silver plated copper wire to the shield.

Cut-off semi-rigid coax cable with ground lead as improvised GHz probe

The result doesn’t look nearly as fancy as the commercial solution, but it’s cheap and easy to make. However, I’d like to point out that I was not doing anything fancy with this makeshift probe and cannot really give a performance feedback. Directly connected to a frequency counter, I could successfully probe a 1.4 GHz and a 2.8 GHz signal. I will try to probe the LOs of C- and Ku-Band LNBs shortly and post back how well that worked. But for less than $1 investment, this is certainly a nice thing to try, though. Links and Sources: [1] PP066 High Bandwidth Passive Probe, Teledyne LeCroy: http://teledynelecroy.com/ [2] Semi Rigid Cable, eBay: http://www.ebay.com/ ## Review: Analog Devices ADF4351 Frequency generation is usually a very critical part in every RF design. The higher the target frequency, the higher complexity. Usually. With the ADF4351, Analog Devices offers an effort-saving component level solution for frequencies up to 4.4 GHz. The ADF4351 from Analog Devices (ADI) is a modern wideband PLL synthesizer with integrated low phase noise VCO. It is capable of generating signals between 35 MHz to 4400 MHz with a very low jitter of typical 0.3 ps. ADI agreed to send me the EVAL-ADF4351EB1Z, an evaluation board for the ADF4351, for review purposes. Let’s check it out! The ADF4351 has an integrated voltage-controlled oscillator (VCO) with a fundamental output frequency ranging from 2200 MHz to 4400 MHz. In addition, divide-by-1/-2/-4/-8/-16/-32/-64 circuits allow the user to generate RF output frequencies as low as 35 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable. An auxiliary RF output is also available, which can be powered down when not in use. Control of all on-chip registers is through a simple wire interface. The device operates with a power supply ranging from 3.0 to 3.6 V and can be powered down when not in use. ADF4351 evaluation board ADI ships the EVAL-ADF4351EB1Z with a USB cable and a CD. The CD contains all software necessary to get started right away. The board itself makes a very clean impression. Despite the surface mount technology, all case styles of the components used can comfortably be handled with appropriate hand soldering tools. This allows for easy application specific modifications. There are two 4 mm jacks for power (3.75 V to 5.5 V), a small USB connector, and 3 SMA connectors on the board. The first SMA connector serves as reference input for an external reference signal. Alternatively, it can be used as an output for the on-board reference (25 MHz). The other two SMAs are the primary RF output of the ADF4351. It is a differential pair. For best performance, make sure to terminate both outputs correctly (50 Ohms) even if just one output is being used. Power can either be supplied through the 4 mm banana jacks or the USB port. Switches S1 and S2 are used to select the power source. Switch S1 is used to power the ADF4351 from the external DC connector and switch S2 to power from the USB port. The USB clock can cause spurs in the RF signal if power is derived from the USB port. Plenty of test points on the board allow easy troubleshooting. An additional 100 mil / 2.54 mm header can be populated to gain easier access to the most important logic signals. The external loop filter on the eval board has a bandwidth of 35 kHz. This value can easily be changed by changing the value of the corresponding components. The software package ‘ADIsimPLL’ from Analog Devices is a great tool for designing an application specific loop filter. Make sure to install the software from the CD before connecting the evaluation board to the PC for the first time. Once the software is installed properly, connect the board to the PC and start the ADF4351 software package. If the two power LEDs on the board (D5 and D6) do not light up upon connection, verify S1 and S2 for proper selection of the desired power source. ADF4351 Application Software The software is self-explanatory. It allows accessing and manipulating of all functions and registers of the ADF4351. Additionally, the software allows you to use the evaluation board as a sweep generator and it can do frequency hopping between two frequencies. After trying this board out for a while, I highly recommend this chip. It is small, inexpensive ($8.25, 100 QTY) and extremely simple to integrate.

I can think of many applications for the ADF4351 in the amateur radio community. The ADF4351 a perfect 21st century alternative for older SP5055 based designs. The SP5055 was a very popular synthesizer chip used in many older amateur radio projects.

The chip is predestined to be used as a flexible Local Oscillator (LO) in amateur radio transverters. A flexible LO frequency allows to cover more bandwidth in the target frequency range than the IF transceiver itself offers. Paired with a baseband processor and a power amplifier, this chip easily transform into an inexpensive amateur television (ATV) transmitter. I will show some practical designs and applications in future articles. Stay tuned!

[3] Evaluation Board User Guide, ADI: ftp://ftp.analog.com/

## Quick look at a BPSK31 signal

PSK31 is gaining more popularity among amateur radio enthusiasts. It’s extremely small bandwidth and excellent performance in weak signal conditions make this mode perfect for low power HF stations.

PSK31 is a digital transmission mode with just about 31 Hz bandwidth. The signal conveys data at a data rate of 31.25 baud and is extremely robust even in weak signal conditions. 10 – 20 Watts of HF power is usually plenty for this mode. Let’s have a look at a PSK31 signal in the time domain.

PSK31 is used to transfer short text messages. The text that is supposed to be transmitted is being encoded varicode [1] prior to transmission. Varicode implements entropy encoding for lossless data compression. Entropy encoding simply means that characters used most frequently have shorter codes than characters used less often. The characters are seperated by binary ’00′. A space symbol for instance has the varicode ’1′, the character ‘t’ has the varicode ’101′, and the symbol ‘?’ has the varicode ’1010101111′.

The most common type of PSK31 is BPSK31. As the name implies, binary phase shift keying (BPSK) is used for this sub-type. A binary ’0′ causes a phase shift of 180 degrees on the carrier and a binary ’1′ causes no phase shift. At a baud rate of 31.25 baud, this would result in an overall bandwidth of 62.5 Hz. To slash the bandwidth in half, the phase shifting occurs at an amplitude minimum and a raised cosine filter makes sure the amplitude transition is as bandwidth preserving as possible.

The following picture, shot with the Teledyne LeCroy WaveAve 1002, shows the 180 degree phase shift and the smooth amplitude transition:

180 degree phase shift at amplitude minimum of a PSK31 signal

The next picture shows another another section of a BPSK31 signal. The carrier is a 1 kHz tone and the displayed data (starting after the first amplitude transistion) reads ’00101′.

Envelope of a PSK31 signal, carrier: 1 kHz

Here’s another screen capture of a BPSK31 signal. In this case the carrier frequency is 4 kHz and the displayed data seems to be ’10010′.

Envelope of a PSK31 signal, carrier: 4 kHz

Now that you know what a PSK31 signal looks like in the time domain, you can use this information to troubleshoot your PSK31 set-up. Ideally, the output of your transmitter should look exactly like the wave forms shown above. If for instance you send a BPSK31 signal with a carrier frequency of 1 kHz into a radio, which is set to 14.070 MHz upper sideband (USB), you should be able to see a signal at 14.071 MHz with the same signal properties as the signals shown above.

Be careful not to destroy your oscilloscope, they don’t usually enjoy high-power RF straight into their input ports. Make sure to terminate your radio with a proper 50 Ohm load capable of handling the expected RF power. And beware of the voltage levels, a 100 Watts RF signal into a 50 Ohms load already has a rms voltage of ~70 Volts. That is enough for a serious RF burn!

Another BPSK related phenomenon shows the following picture. The carrier frequency is again 4 kHz. The mixed domain mode of the LeCroy WaveAce 1002 is used here to display the signal both in the time domain (top) and in the frequency domain (bottom) at the same time. But where is the peak in the frequency domain? 8 kHz? What is wrong here?

BPSK31 signal with a carrier frequency of 4 kHz. Clearly visible in the frequency domain (bottom) is a phase shift free 2. Harmonic (8 kHz)

The answer is simple: Nothing is wrong here. What the oscilloscope displays in the frequency domain is absolutely spot on. The 8 kHz peak is simply the harmonic of the original BPSK modulated 4 kHz signal.

Because the BPSK causes a phase shift of ± 180 degrees, the phase shift on the second harmonic would be ± 360 degrees. A phase shift of ± 360 degrees is practically equal to no phase change at all. That means the harmonic completely free of any phase modulation whatsoever.

This effect is used in a ‘squaring loop’ to recover the carrier. The received signal is being multiplied with itself (=squared) to generate a signal with twice the frequency of the original carrier but with the phase modulation removed. If the signal is then divided by two, the generated signal is phase-coherent with the original carrier and can be used to recover the data.

[1] Varicode, Wikipedia: http://en.wikipedia.org/wiki/Varicode

## Why PSK31 over FM is nonsense

PSK31 is a digital transmission mode designed for minimum bandwidth and great performance even in weak signal conditions. Sending a PSK31 signal over the air using Frequency Modulation (FM) completely eliminates both the narrow bandwidth and the robustness in weak signal conditions.

PSK31 is a general term for all kinds of M-ary Phase Shift Keying (PSK) modulation schemes with a baud rate of 31.25 baud. This mode is commonly used to transmit short text messages such as a quick description of one’s station. The most common modes are BPSK31 and QPSK31. As the names suggest, BPSK31 uses Binary Phase Shift Keying (BPSK) and QPSK31 uses Quadrature Phase Shift Keying (QPSK). For this article, I am going to focus on BPSK31.

Envelope of a PSK31 signal, carrier: 1 kHz

A BPSK modulated signal with a data rate of 31.25 baud will result in a bandwidth of 31.25 Hz [1]. Generally, most articles speak of 31 Hz because it’s easier to read, write and remember. But this bandwidth is of course only true if you indeed do transmit a BPSK signal, not FM. Now I know what you are thinking, “Why BPSK? I use SSB for PSK31!”

When a transmitter in Single-Sideband (SSB) mode is used and a M-ary PSK (BPSK, QPSK, etc.) signal is applied to the audio input of such said transmitter, the SSB transmitter will merely act as upconverter and emit a M-ary HF signal. If one applies a BPSK modulated 1 KHz tone to the audio input of a SSB transmitter set to 14.070 MHz upper sideband (USB), this will result in a BPSK modulated 14.071 MHz signal. Therefore, the overall bandwidth of the HF signal is equal to the bandwidth of the original BPSK IF (audio signal).

One thing that many amateur radio operators seem to have a problem with is understanding that the audio fed into the transmitter is already a modulated signal. It is not the modulation information, but the modulation information modulated on a carrier already.

180-degree phase shift at amplitude minimum of a PSK31 signal

What happens if a BPSK modulated audio signal is connected to an FM transmitter? Carson’s bandwidth rule should be able to shed some light on this question. Carson’s bandwidth rule is used to determine the bandwidth of a FM signal in which 98% of the energy is contained [2]. The 17 dB bandwidth, so to speak.

$B = 2(\Delta f + f _m)$

B = 17 dB bandwidth (98 %)
Δf = FM deviation
fm = highest frequency in the modulation signal

A normal audio voice signal in most commercial and amateur radio sets is limited to only transmit the range between 400-3000 Hz. Therefore, the maximum frequency we need to consider for bandwidth calculations is 3 kHz.

The FM deviation is around 5 kHz for signals with 25 kHz channel spacing and around 2.5 kHz for 12.5 kHz wide channel spacing (narrowband FM).

Using a normal audio signal with a maximum frequency of 3 kHz, the bandwidth according to Carson’s formula would result in 16 kHz for the 5 kHz deviation and 11 kHz for 2.5 kHz deviation. Please note that the actual bandwidth is wider than this and additional guard band between channels is needed. In a practical set-up an entire 20 kHz channel is occupied.

If a PSK31 modulated audio signal is now used to modulate the FM transmitter, the bandwidth will behave accordingly. Assuming a 1 kHz audio carrier, the resulting FM bandwidth will be 12 kHz for 5 kHz deviation and 7 kHz for 2.5 kHz deviation. Since most amateur radio sets have a deviation of 5 kHz, let’s stick with the 16 kHz bandwidth.

That means our resulting FF signal is 19,968.75 Hz wider than necessary. Or in other words: the resulting signal is occupying 64000 % of the necessary bandwidth. But that’s not all, the weak signal advantages disappear now, as well. This is because they will stay the same as the weak signal capabilities of a “regular” FM signal. Therefore, conclusively PSK31 over FM is nothing but a reductio ad absurdum. Or, in plain English, nonsense.

I think the reason why PSK31 over FM is becoming so popular is because few understand what they are actually doing and what is going on inside their radio. For most, it’s just “you connect your sound card to your radio and you have this super cool digimode, it’s that simple.” Well, quite obviously, it’s not that simple.

Now I am sure a few people will complain about this article and say PSK31 over FM is still useful to get a taste of PSK31 and to get your feet wet. No, you don’t test drive a bicycle to see how flying an air craft feels like either. In the same fashion, I doubt anyone would seriously pursue doing CW over FM by keying an audio tone off and on (other than for CW training purposes).

And last but not least, if you decide to actively participate in this nonsense, at least get your facts straight. You did not do “PSK31,” you had an FM QSO, nothing else. Your QSL cards, QRZ.com log book entries, etc. need to read FM, not PSK31. However, your emission designator changes from F3E (FM voice) to F3D (FM data).

[1] M-ary PSK calculator, KF5OBS: http://jaunty-electronics.com/

[2] Carson bandwidth rule, Wikipedia: http://en.wikipedia.org/

## DSSS / BPSK Clock Recovery with the Abracon ABFT

Clock recovery in Spread Spectrum applications and BPSK modulated signals can be somewhat tricky. There are no commercial solutions available solely for this task either. Or are there? This article shows a great off-label use of the Abracon ABFT.

Clock recovery in a Direct Sequence Spread Spectrum (DSSS) receiver can be quite a challenge. Because the clock recovery is crucial, this part of the receiver naturally determines the overall performance of the receiver. The Abracon ABFT, which I reviewed in a previous article, might be just the right Commercial Off-The-Shelf (COTS) device to get this job done.

There are two common approaches to recover the clock of a Direct Sequence Spread Spectrum (DSSS) signal, or BPSK modulated signals in general, for that matter. The first one is called a squaring loop and the second one is called a Costas loop.

The first technique relies on the fact that because the BPSK modulation causes ±180° phase transitions, the squared signal will have phase transitions of ±360°. The squared signal has now twice the frequency of the original carrier. If this signal is then being divided by two, the output signal will be phase coherent with the original carrier. BPSK and DSBSC signal carriers can be recovered in this fashion.

While this approach is mathematically the simplest, the practical implementation faces some hardships in the actual circuit designs.

The Costas loop is a PLL-based approach using an I/Q demodulator and two individual loops to control a single VCO [1]. The design is rather complex and I am not going into any detail here.

While I was reviewing the Abracon ABFT frequency translator / jitter attenuator, I was immediately curious if this device could lock onto the carrier of a BPSK modulated direct sequence spread spectrum signal. Why did I think it would work?

My first thought was that BPSK modulation can in a way be thought of as jitter. Remember, jitter is the undesired deviation from true periodicity of an assumed periodic signal. If you take a close look at the following BPSK modulated signal in the time domain, you can see where I am getting this idea.

10 MHz carrier (top trace) and BPSK modulated signal (bottom trace)

My second thought revolved around the symmetry of a BPSK modulated signal. The power density of the BPSK modulated DSSS signal is the strongest around the original carrier frequency and declines from there off to the sides. The following picture shows that very well.

DSSS spectrum (Carrier: 10 MHz, PRBS Clock: 5 MHz)

So the key question is: does the Abracon ABFT lock onto the carrier of a BPSK modulated DSSS signal? Well, the only way to find out is to try it!

In this experiment, I am using the same 127-bit Pseudo Random Number Generator (PRNG) that I have used in my previous article in which I took a closer look at a DSSS signal and its properties.

A pseudorandom number generator (PRNG) with simple XOR-based mixer

In my complete test setup I am using a LeCroy WaveStation 2052 waveform generator for the carrier, a Rigol DG1022 for the Pseudo Random Binary Stream (PRBS) clock rate, a TTi TF930 frequency counter and the LeCroy WaveStation 1022 for visualization. The two signal generators and the frequency counter are synchronized to a 10 MHz GPS-disciplined oscillator for highest accuracy and precision possible.

Here’s a blog diagram of my setup:

Block diagram of my test setup

The whole setup became a bit messy but ah well, it got the job done!

This is what the quick and dirty test setup looked like

Without anything connected to its input, the Abracon ABFT did put out a signal that is slightly below 20 MHz. Once I connected the DSSS signal, the ABFt immediately locked up and started to put out a rock solid 20 MHz signal. That’s right, not even 1 or .1 Hz off frequency! Now, how cool is that?

The TF930 says 20.0000000 MHz exactly

A closer look at the signal in the time domain proves that the output of the ABFT is twice the original carrier frequency, but otherwise phase coherent.

Original 10 MHz carrier (top trace) and recovered carrier from the ABFT’s output (bottom trace)

There is a bit of a delay on the bottom trace, but this is expected simply due to the higher delay in the physically longer signal path.

This article proves that it is often worth to think outside the box. Abracon did not design this device for this purpose in any way. There are many parts and pieces out there which can be used for all kinds of things they were not originally designed for.

So where do we go next? Well, I would love to bring this 10 MHz BPSK / DSSS demodulator in the shape of a single PCB and experiment further with it in an actual over the air application. Additionally, I would love to take a look at how well the ABFT does with QPSK and other M-ary PSK modulation. I did ask Abracon to supply some of those modules for the purpose of using them experimental PCB designs. I am hopeful they will respond positively to the request. Stay tuned!

[1] Costas Loop Implementation with Hypersignal Block Diagram/RIDE, National Instruments http://www.ni.com/

## Review: Abracon ABFT Frequency Translators

In March, 2012, Abracon announced the production of ultra-low jitter, VCXO based frequency translators / jitter attenuators. This is supposed to resolve some problems that accompany classic PLL-based designs at an affordable price. Now, the ABFT frequency translators / jitter attenuators are available on the market and it’s time to have a closer look.

The Abracon ABFT frequency translators / jitter attenuators are available as 20 MHz and 40 MHz versions. They both require a 10 MHz reference frequency input, have an ultra small footprint (5.00 x 7.00 mm) and only consume 14 mA under lock. Abracon sent me an evaluation board for the 20 MHz version. Let’s check it out!

Close-Up view of the Abracon ABFT eval board (20 MHz version)

Before we dive in, let’s talk about clock multiplication using a classic PLL design. To talk about the problems associated with classic PLL multiplier circuits, here is a simple 10 MHz to 20 MHz multiplier circuit:

Simple frequency doubler using a classic PLL based approach

I am intentionally mixing block diagram symbols and actual circuit drawing symbols for clarity. The VCOs output signal is divided by two using a D type flip flop. If the VCO frequency is exactly 20 MHz, the output of the D flip flop is 10 MHz. The output of the flip flop is then compared to the 10 MHz reference by a simple XOR gate based phase detector. How an XOR gate based phase detector works has been explained in one of my previous articles.

A big problem with that circuit (and most PLL designs for that matter) is the following: if the input signal is exactly 10 MHz with absolutely no jitter, everything works well. The phase noise performance of the output would then primarily depend on the used VCO. The problem is, jitter free signals simply don’t exist in the real world. Remember, jitter is the undesired deviation from true periodicity of an assumed periodic signal. Jitter can be observed in several of the signal parameters. Troublesome for this circuit are phase and frequency errors. We will talk about frequency errors only as every phase error forcibly causes instantaneous frequency errors.

Let’s assume the input signal jumps between 9,999,990 Hz and 10,000,010 Hz. Our PLL circuit is now doubling this error because it is a fixed x 2 multiplier. The jitter on the output signal will therefore essentially be twice the jitter on the input frequency. The output frequency will therefore jump between 19,999,980 Hz to 20,000,020 Hz. This condition is quite obviously undesirable.

A possible workaround is to increase the time constant of the loop-filter (R1 + C1). If overdone, the PLL will turn into a Frequency Locked Loop (FLL) and it will no longer be able to react to quick changes in phase and frequency differences. While this reduces the aforementioned problem drastically, the big loop time introduces a new problem. The loop is now too slow to correct errors quickly enough to have a reliable output signal. Additionally, the lock-time is increased significantly. Both are of course undesirable conditions.

Needless to say, designing such a PLL can be a big pain in one’s proverbial behind when there are heightened phase noise / jitter requirements on the table. It’s simply nothing that can be accomplished with your common 4046 CMOS or similar. So instead of trying experiment with different loop filters and trying to find the ‘right’ trade-off of loop properties for hours on end, why not grab something off the shelf that works right away? And that takes us right back on topic of the Abracon ABFT frequency translator.

Abracon ABFT frequency translator / jitter attenuator evaluation board

Here are the tech-specs straight from the datasheet [1]:

• 5x7x2 mm SMT, RoHS Compliant reflow-able package
• +3.3V Supply Voltage
• Temperature Range: -40ºC to +85ºC
• LVCMOS Output
• Frequency Stability Over the Whole Temperature Range: ± 25 ppb
• Supply Current Under Lock: < 14 mA
• Rise Time: < 1.2 ns
• Stand Alone Aging (10 years): + 12 ppm

To make the evaluation and experimentation process simpler, Abracon offers a small evaluation board for the ABFT [2]. The board’s dimensions are about 40 x 30 mm. Equipped with 3 industry standard SMA connectors (Reference in, Vdd, and RF Out), the board can quickly be implemented in test setups.

But that’s enough text for now. It’s time to look at some pictures. I used the ABPSM-ULN-A ultra low noise power supply module and the Abracon Sync ‘n Go together with the ABFT eval board in my test setup.

My test setup: The ABFT is connected to a Sync ‘n Go 10 MHz reference and an ultra low noise power supply using high quality coaxial cable

The first thing we’re going to have a look at is the output waveform. I am using the LeCroy WaveAce 1002 for the following two screenshots.

Output of the ABFT 20 MHz in the time domain

Shape, voltage and frequency look good. There’s a bit of ringing due to an impedance mismatch between the probe and the ABFT. The overshoot is caused by the impedance mismatch, as well. You might note that the rise time measured by the WaveAce is higher than what the ABFT’s datasheet claims. But no need to worry — what’s displayed here is the rise time of the LeCroy WaveAce 1002 as shown in my review. I simply do not have a scope that is capable of dealing with 1.2 ns rise time.

Output of the Abracon ABFT 20 MHz frequency translator on a LeCroy WaveAce oscilloscope. Top: Time domain, Bottom: Frequency domain

No surprise in the frequency domain either. Because an ideal rectangular signal is made up of sine waves of the fundamental frequency and uneven multiples of the fundamental frequency, the uneven harmonics displayed on the WaveAce 1002 are stronger than the even ones.

Now it’s time to look closer at the phase noise performance. Signal source analyzers are extremely expensive. That’s why I do not have one available to me. However, Abracon’s Syed Raza (Director of Engineering, Abracon Corporation) supplied proof for the phase noise performance without hesitation. He is also using the ABPSM-ULN-A ultra low noise power supply module and the Abracon Sync ‘n Go together with the ABFT eval board in his setup. The output of the ABFT eval board is fed into an Agilent E5052A signal source analyzer.

Setup to test the phase noise performance of the ABFT using an Agilent E5052A Signal Source Analyzer

The phase noise performance measured by the E5052A is at any given marker point better than what is mentioned in the datasheet. The black line is the phase noise of the ABFT and the blue line is a 10 MHz Stratum III reference.

Phase noise performance of the 20 MHz ABFT measured with an Agilent E5052A Signal Source Analyzer

The datasheet has some additional phase performance screenshots. Abracon shows for instance what happens when the input of the ABFT is fed with a dirty crystal oscillator. The phase noise is significantly improved.

Abracon suggests that the device is suitable for use in Telecom applications such as base station equipment, broadband modems, DSLAMs and base stations.

I can think of much simpler applications than that. For instance, 20 MHz and 40 MHz are both common clock frequencies for microcontroller. If a high precision requirement or simply the need to synchronize the MCU application to an external 10 MHz reference arises, this is pretty much the simplest way to go.

It is noteworthy that the ABFT still puts out a valid signal in free running mode if no reference input signal is present. Therefore, the ABFT would be very suitable for applications where a free-running mode is desired as well as the option to sync the device to a more accurate 10 MHz reference signal when required. I personally can see myself using this feature in future microwave synthesizer designs.

Mouser has both the 20 MHz and the 40 MHz versions in stock for $26.30 per piece [3]. That price is for single quantities. The price drops to$21.04 per piece for 500 ABFT modules. Reels are available with 250 or 1000 units per reel.

[1] Abracon ABFT Datasheet, Abracon: http://www.abracon.com/

[2] Abracon ABFT Evaluation Board, Abracon: http://www.abracon.com/

[3] Abracon ABFT 20 MHz, Mouser Electronics: http://www.mouser.com/

## Closer look at a Direct Sequence Spread Spectrum Signal

This article is going to take a closer look at the properties of a pseudo random bit sequence and a simple direct sequence spread spectrum signal both in the time- and frequency domain using the FFT capabilities of a Teledyne LeCroy WaveAce 1002.

A while back, I posted an article about a Pseudorandom Number Generator (PRNG) for Direct Sequence Spread Spectrum (DSS) experiments. PRNGs are the key element in many cryptographic applications and they also play a major role in DSSS.

To generate a pseudorandom binary sequence (PRBS), I am using a linear feedback shift register (LFSR). A LFSR is a shift register of which the input bit is a linear function of its previous state. Usually two or more bits of the overall shift register value are exclusive-OR-ed and fed back into the shift register. The bit positions that affect the next state are called the taps.

A pseudorandom number generator (PRNG) made up from a a CMOS 4015 shift register and a 4030 XOR gate ugly construction style (aka ‘dead bug’ or ‘Mahatten style’)

The next picture shows a simple 7 stage PRNG which I am using for the following experiments. A 7-stage shift register can produce a code with a maximal length of 27-1 = 127 code bits. The output sequence almost equals the statistical expectation for a truly random sequence. The numbers have a nearly perfect bell-shaped Gaussian distribution. However, LFSR is deterministic. If any given status of the shift register is known, the next state can be predicted.

A pseudorandom number generator (PRNG)

Here is an example output of the PRNG made up out of 5 individual screenshots:

Animated screenshot of the PRNG output made up out of 5 still screenshots.

We wouldn’t expect the output frequency to be larger than the clock rate at any point. To confirm this, I am using an eye diagram with infinite persistence. And sure enough, the smallest period length occurring in the output signal is 100 ns (≙ 10 MHz).

Eye diagram of a 127 bit pseudorandom bit sequence

From 0 – 10 MHz, we can see half of a bell curve with its peak at 0 MHz. And as expected, due to the rich content of harmonics of the rectangular signal, we can clearly see a bell shape ranging from 10 to 20 MHz with a peak at 15 MHz. There is another bell shape ranging from 20 to 30 MHz with a peak at 25 MHz.

Output spectrum of a 127 bit pseudorandom number generator (PRNG)

Zooming in on the 20 to 30 MHz range shows that the distribution looks pretty close to what we expect.

Output spectrum of a 127 bit pseudorandom number generator (PRNG)

The next picture shows the bell shapes pretty clearly. It also shows how the bell shapes to the right decrease in amplitude as the harmonics are weakening.

Output spectrum of a 127 bit pseudorandom number generator (PRNG)

To get an idea what an actual DSSS signal looks like, we are going mix a PRBS with a constant carrier. Normally, some transmit data would be XORed with the PRBS before transmission. But for the sake of this experiment, we don’t need any data other than the code sequence (PRBS) itself.

Just like in a real DSSS application, we are going to use an XOR gate as mixer. Essentially, this results in the carrier being modulated with the code sequence (PRBS) using Binary Phase-Shift Keying (BPSK). This is because the XOR will invert (= 180 degree phase shift) the phase relation of the carrier if the modulation input is ‘high’ (logical 1).

A pseudorandom number generator (PRNG) with simple XOR-based mixer

So how does the BPSK modulated look like in the frequency domain? There are only a few pictures of DSSS signals available on the web and in literature. Additionally, the quality of those pictures isn’t very good. Let’s ask the WaveAce 1002 scope for help again.

But before we jump into the frequency domain, let’s look at the BPSK signal in the time domain.

10 MHz carrier BPSK modulated with the PRBS signal (clocked at 1 MHz). Clearly visible, the 180 degree phase jump on the right.

For comparison, here is a picture of the unmodulated 10 MHz carrier in the time domain. Other than the 10 MHz carrier, there’s only noise visible.

Spectrum of the 10 MHz carrier without any modulation

Next, I am going to modulate the carrier with the pseudo random binary sequence. The clock rate of the PRNG is 5 MHz. What do we expect to see? First, we can assume the bandwidth to be 10 MHz. This is because the bandwidth of a BPSK signal is equal to two times the (max.) data rate [1].

Second, the shape can be determined from a theoretical standpoint as well. The XOR mixer adds and subtracts the modulation signal to / from the carrier. Since we know how the output spectrum of the PRNG looks, the shape can be assumed as well. From the addition, we expect to see half of a bell shape starting at 10 MHz and flooring at 15 MHz. Some bell shaped 5 MHz humps should appear directly after that. The subtraction will yield the exact same result, except mirrored around the X-axis starting from the 10 MHz carrier. That would be half of a bell shape starting from 5 MHz and peaking at 10 MHz. Side lobes will appear left from the 5 MHz point with a bandwidth of 5 MHz each. Since negative frequencies don’t exist, there is actually just room for one side lobe in this scenario.

Too much theory? I agree, here’s a pretty picture of the 10 MHz carrier modulated with the code stream clocked at 5 MHz.

DSSS spectrum (Carrier: 10 MHz, PRBS Clock: 5 MHz)

And we see exactly what we’d expect. Awesome! In case the theoretical description of the signal was a bit to difficult to follow, try it again with the picture as help. A picture makes so many complex issues much clearer. That’s why pictures are so much more effective than text and an oscilloscope is such a powerful tool.

Next up is a picture of the 10 MHz carrier modulated with the code stream clocked at 2.5 MHz. Since the clock rate is half as much in the previous pictures, we’d consequently expect the lobes to be half as wide. The main lobe should have a width of 5 MHz and the side-lobes should be 2.5 MHz wide.

DSSS spectrum (Carrier: 10 MHz, PRBS Clock: 2.5 MHz)

The last picture shows the 10 MHz carrier modulated with the code stream clocked at 1 MHz. The main lobe should have a width of 2 MHz and the side lobes should be 1 MHz wide.

DSSS spectrum (Carrier: 10 MHz, PRBS Clock: 1 MHz)

It seems that also this time reality fits the theory. Or the other way around? Ah well, they fit!

In a practical application, the bandwidth of the transmitted signal would of course have to be limited for spectrum efficiency. Interestingly, not all of the main lobe is needed to reliably transport data. To be precise, the overall bandwidth of the transmitted signal can be cut down to be equal to the maximum data rate. This is called the Nyquist bandwidth.

In the case of the 5 Mbps PRBS stream, we could cut the main lobe off to be only 5 MHz wide. This is being done with a raised-cosine filter in a real world application. This is not only true for direct sequence spread spectrum applications but for all digital phase shift keying modes such as BPSK, QPSK, and 8PSK.

I wrote this article for two reasons. The first one being the obvious reason, to show some properties of a DSSS signal. The second reason is that I wanted to show what a powerful tool an oscilloscope is. The LeCroy WaveAce is a entry-level sub \$1000 scope [2], yet it mastered the complex tasks in this article with flying colors.

One thing you might have noticed is that I am using an extremely large time base when displaying a FFT of the signal. You can’t tell any signal properties (except amplitude) of the signal in the time domain anymore. All that’s left is a yellow brick. This is intentional. Most scopes logically only perform the FFT on the samples displayed. Since the frequency components of the DSSS signal change rapidly, we need the maximum amount of samples possible. Care needs to be taken to not overdo it, though, else the scope will display an incorrect lower frequency. This effect is called aliasing and occurs in all sampling systems [3].

Update (11/08/2012): I have received an email asking about what the clearly visible spur at 20 MHz is. If you look at the following picture of the DSSS signal again, you can clearly notice the spike at 20 MHz.

DSSS spectrum (Carrier: 10 MHz, PRBS Clock: 5 MHz)

What is it and where does it come from? It is simply the harmonic of the original BPSK modulated 10 MHz signal. Because the BPSK causes a phase shift of ± 180 degrees, the phase shift on the second harmonic would be ± 360 degrees. A phase shift of ± 360 degrees is practically equal to no phase change at all. That means the harmonic completely free of any phase modulation whatsoever. This effect is used in a squaring loop to recover the carrier. The received signal is being multiplied with itself (=squared) to generate a signal with twice the frequency of the original carrier but with the phase modulation removed. If the signal is then divided by two, the generated signal is phase-coherent with the original carrier and can be used to recover the data.